1. Field of the Invention
Embodiments of the present invention relate to a method for manufacturing integrated circuit devices. More particularly, embodiments of the invention relate to a system and process of utilizing ALD tantalum nitride layer in the formation of metal interconnect structures.
2. Description of the Related Art
As the structure size of integrated circuit (IC) devices is scaled down to sub-quarter micron dimensions, electrical resistance and current densities have become an area for concern and improvement. Multilevel interconnect technology provides the conductive paths throughout an IC device, and are formed in high aspect ratio features including contacts, plugs, vias, lines, wires, and other features. A typical process for forming an interconnect on a substrate includes depositing one or more layers, etching at least one of the layer(s) to form one or more features, depositing a barrier layer in the feature(s) and depositing one or more layers to fill the feature. Typically, a feature is formed within a dielectric material disposed between a lower conductive layer and an upper conductive layer. The interconnect is formed within the feature to link the upper and lower conductive layers. Reliable formation of these interconnect features is important to the production of the circuits and the continued effort to increase circuit density and quality on individual substrates.
Copper is a choice metal for filling sub-micron high aspect ratio interconnect features because copper and its alloys have lower resistivities than aluminum. However, copper diffuses more readily into surrounding materials and can alter the electronic device characteristics of the adjacent layers. The diffused copper can form a conductive path between layers thereby reducing the reliability of the overall circuit and may even result in device failure. Hence, barrier layers are deposited prior to copper metallization to prevent or impede the diffusion of copper atoms. Barrier layers typically are refractory metals such as tungsten, titanium, tantalum, and nitrides thereof, which all have a greater resistivity than copper.
To deposit a barrier layer within a feature, the barrier layer is typically deposited on the bottom of the feature as well as the sidewalls thereof. Adequate deposition of the barrier layer on sidewalls typically results in excess deposition on the bottom. The excess amount of the barrier layer on the bottom of the feature not only increases the overall resistance of the feature, but also forms an obstruction between higher and lower metal interconnects of a multi-layered interconnect structure.
There is a need, therefore, for an improved method for forming metal interconnect structures which minimizes the electrical resistance of the interconnect.